Generally, the speed at which an integrated circuit operates is influenced by the distance between the farthest separated components that communicate with each other on the chip. Laying out circuits as three-dimensional structures has been shown to significantly reduce the communication path length between on-chip components, provided the vertical distances between the layers are much smaller than the chip width of the individual layers. Thus, by stacking circuit layers vertically, the overall chip speed is typically increased. One method that has been used to implement such stacking is through wafer bonding.
Wafer bonding is the joining together of two or more semiconductor wafers on which integrated circuitry has been formed. Wafers are typically joined by direct bonding of external oxide layers or by adding adhesives to interlayer dielectric (ILD) layers. The bonded result produces a three-dimensional wafer stack which is subsequently diced into separate “stacked dies”, with each individual stacked die having multiple layers of integrated circuitry. In addition to the increased speed that the three-dimensional circuitry typically experiences, wafer stacking offers other potential benefits, including improved form factors, lower costs, and greater integration through system-on-chip (SOC) solutions. In order to enable the various components integrated within each stacked die, electrical connections are provided that provide conductors between vertical layers. Through silicon vias (TSVs) are typically fabricated to provide vias filled with a conducting material that passes completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers.
In an existing TSV formation process, TSVs are formed after the CMOS device formation in a wafer substrate or even after the top metallization process. One disadvantage of forming TSVs after the CMOS process or metallization process is that the density of vias is typically less because of etch and design limitations. Etching through metallization layers does not typically result in a recess that would allow for a particularly dense TSV. Moreover, again because the process etches through metallization and contact regions, the design of the via is limited based on the existing structures of the metallization layers and contact regions. Thus, designers will typically have to design the TSV network around the existing metal layers and contact traces. This limited design and density potentially creates connection, contact, and reliability problems.
A further limitation to the existing TSV formation process is the limited depth to which TSVs may be formed in a wafer substrate. Due to the existing structures of the metallization layers, an etch process typically employed to form TSV openings in a wafer substrate proceeds in a wafer substrate to a limited depth that is significantly less than a substrate thickness. As an example, a typical plasma etch process may be used to form TSV openings with depth of from about 25 to about 50 microns, compared with a typical silicon wafer substrate of about 700 microns. Back grinding is typically used in thinning the wafer substrate to a thickness of less than 100 microns, and exposing the TSVs in order to connect stacked dies. However, this practice may significantly reduce the mechanical strength of a wafer substrate as a solid foundation for the integrated circuit (IC) formed thereon. Moreover, an overly-thinned wafer substrate is prone to breakage, thus significantly impacting the overall IC product yield.